The present invention relates to integrated circuits, and more particularly to integrated circuits comprising memories.
FIG. 1A is a top view of a dynamic random access memory array (DRAM array). FIG. 1B shows a planar vertical cross section of the array along a bitline, along a line I-I′ in FIG. 1A. Each DRAM cell includes a storage capacitor having a plate 120 formed in a trench 124 in a P type semiconductor substrate 130. The other capacitor plate 134 is a buried N+ region of substrate 130. The capacitor regions 134 are interconnected by an N+ doped band region 140 held at a constant voltage during the memory operation. Dielectric film 144 on the trench surface separates the capacitor plates 120 from N type regions 134, 140 and an overlying P well 150 of substrate 130. Dielectric 144 is removed from the trench sidewall in a contact area 160 in which the capacitor plate 120 physically contacts an N+ doped buried strap region 164 of substrate 130. Buried strap 164 extends from the trench sidewall to a source/drain region 170 of the cell's pass transistor. Pass transistor gates 174 are provided by a polysilicon wordline (FIG. 1A) running through the array. The same numeral 174 is used for the wordlines and the individual gates. The other source/drain region 180 of the pass transistor is connected to a bitline 184 (schematically shown as a straight line in FIG. 1A) by a contact 186 (shown as a dot in FIG. 1A). Region 184 and contact 186 are shared with the pass transistor of the adjacent cell in the same column. The bitlines are connected to sense amplifiers (not shown) as known in the art. See e.g. U.S. Pat. No. 6,440,794 issued on Aug. 27, 2002 to Kim and incorporated herein by reference.
The cells of each column are grouped in pairs. Each trench 124 has sides 124.1, 124.2, with the side 124.2 facing the other cell of the same pair, and the side 124.1 facing away from the other cell of the pair. The cell pairs of each column are shifted relative to the cell pairs of the adjacent columns. In each column, two pass transistors are located between the adjacent cell pairs. Each wordline 174 provides pass transistor gates for alternating columns, and runs over trenches 124 of the remaining columns. Dielectric 188 provides insulation between the trenches 124 in each cell pair at the top of substrate 130 and also helps insulate the capacitor plates 120 from the overlying wordlines 174. Dielectric regions 192 (FIG. 1A) are manufactured with shallow trench isolation technology (STI) to provide substrate isolation between the adjacent memory columns.
FIG. 2 illustrates the memory array cross section at an intermediate fabrication stage. A silicon dioxide layer 210 (“pad oxide”) and a silicon nitride layer 220 are formed on substrate 130 and patterned photolithographically to define trenches 124. Substrate 130 is etched to form the trenches 124. Arsenic doped silicon dioxide (also called arsenic doped silicon glass or ASG), not shown, is deposited into the bottom portions of the trenches 124. The structure is heated to diffuse the arsenic into substrate 130 and form the capacitor plates 134. Dielectric 144 and doped polysilicon 120 are formed in the trenches 124. Dielectric 144 has been removed at the top of the trenches 124 and, in particular, in contact areas 160. Therefore, polysilicon 120 physically contacts the silicon substrate at the top of the trenches 124.
A mask 310 (FIG. 3) is formed over the structure to protect the polysilicon 120 near contact areas 160. Nitride 220, oxide 210, polysilicon 120 and substrate 130 are etched through the mask openings to form a region 320 in each pair of the memory cells. Isolation trenches for dielectric regions 192 (FIG. 1A) can be etched in substrate 130 at the same time or in a separate step. Mask 310 is removed, and dielectric 188 (FIG. 4) is deposited and polished to fill the regions 320 and the isolation trenches.
Dielectric 188 is polished down to a desired depth. See FIG. 1B. Oxide 210 and nitride 220 are removed. Band region 140 is formed by ion implantation. Wordlines 174, source/drain regions 170 and 180, buried straps 164, and bitlines 184 are then formed.
New techniques for memory cell isolation are desirable. The new techniques should preferably facilitate fabrication of downsized memories.